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  description AMS2319 0 is 0 the 0 pchannel 0 logic 0 enhancement 0 mode 0 power 0 field 0 effect 0 transistor 0 is produced using high cell density, dmos trench techn ology. this high density process is especially tailored to minimize onstate resista nce. these devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits where highside switching and low inline power loss are required in a very small outline surface mount package. pin configuration sot-23 1.gate 2.source 3.drain part marking sot-23 y: year code w: week code feature  40v/3.5a, r ds(on) = 75m (typ.) @vgs = 10v  40v/2.8a, r ds(on) = 105m @vgs = 4.5v  super high density cell design for extremely low r ds(on)  exceptional onresistance and maximum dc current capability  sot23 package design 3 1 2 d g s 3 1 2 19yw
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b b electrical characteristics ( ta = 25 p unless otherwise noted ) parameter symbol condition min typ max unit static drain source breakdown voltage v (br)dss v gs =0v,i d =10ua 40 v gate threshold voltage v gs(th) v ds =vgs,i d =250ua 0.8 1.5 v gate leakage current i gss v ds =0v,v gs = 20v 100 na zero gate voltage drain current i dss v ds =36v,v gs =0v 1 ua v ds =36v,v gs =0v t j =85 p 5 onstate drain current i d(on) v ds p 5v,v gs =4.5v 3.5 a drainsource onresistance r ds(on) v gs = 10v,i d = 3 . 0 a v gs =4.5v,i d =2.8a 0.075 0.105 p2 forward transconductance g fs v ds =15v,i d =3.0a 13 s diode forward voltage v sd i s =1.3a,v gs =0v 1.0 v dynamic total gate charge q g v ds =15v v gs =10v i d p 3.0a 9 12 nc gatesource charge q gs 1.5 gatedrain charge q gd 2.0 inp ut capacitance c iss v ds =15v v gs =0v f=1mh z 500 pf output capacitance c oss 95 reverse transfer capacitance c rss 50 turnon time t d(on) tr v dd =15v r l =15 p2 i d =1.0a v gen =10v r g =6 p2 8 20 ns 10 20 turnoff time t d(off) tf 30 35 15 20
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